The present invention relates to methods and apparatus for forming semiconductor devices, and in particular, to forming an antifuse in an integrated circuit.
Integrated circuits (ICs) contain antifuses to selectively connect electrical nodes on an IC. One type of antifuse, as shown in the prior art semiconductor cross section of FIG. 1, is typically formed in an integrated circuit (IC) over active device areas, defined by field oxide 106, and separated from other conductive layers by an insulating material 108. The structure of an antifuse is similar to that of a capacitor. Antifuses contain a programming layer 110, sandwiched between two conductor layers 112 and 114. The programming layer 110 typically comprises a dielectric material, amorphous silicon, and/or a barrier metal, which prevents unwanted diffusion of material between the conductor layers 112 and 114.
Antifuses have a very high resistance in the unblown state, essentially forming an open circuit. In the blown state, it is desirable for antifuses to have a low resistance. To program an antifuse, as shown in FIG. 1, a high voltage is applied across the conducting layers 112 and 114. The high voltage causes dielectric layer 110 to breakdown, which forms a conductive path through the antifuse.
An inherent problem associated with antifuses is that high resistance is desired in the unblown state and very low resistance is desired in the blown state. It is difficult to form an antifuse with a high resistance in the unblown state, and then obtain a consistently low resistance value once an antifuse is turned programmed or blown. FIG. 2 shows the various components of the overall antifuse resistance, when it is in the unblown state. Resistance from n(+) regions 120, as shown in FIG. 1, formed where connections 122 are made to the substrate 124, have an associated resistance, shown as 218 in FIG. 2. Resistance from an n(xe2x88x92) region 126, over which the antifuse is formed, is shown as 228 in FIG. 2. Other components of the antifuse resistance comprise resistance 230 from the bottom conductor layer 112, resistance 232 from the top conductor layer 114, contact resistance 234 from the contact 122 to the top conductor layer 114, and resistance 236 from a transistor, which activates current through the antifuse. Capacitance 238 from the programming layer 110 has an effect on the voltage required to program the layer 110. A higher capacitance 238 due to a thinner dielectric results in a lower voltage required to program the layer 100. Once an antifuse is programmed, the highly resistive capacitance element 238 is replaced by a programmed layer resistance value, which is added to an antifuse""s total resistance in the blown state.
Due to the large number of components which contribute to antifuse resistance, as ICs are becoming more dense and devices are required to perform more functions at a faster rate, it is critical that resistance be decreased throughout the antifuse. Lower antifuse resistance enables device functions to be performed faster, both when programming an antifuse and when a programmed antifuse is a component in an IC. For example, antifuses are currently used in dynamic random access memory (DRAM) cell arrays to actively connect redundant memory cells in place of defective cells, typically on a row or column basis. If antifuses are used for row or column redundancy, they may lie in a speed path and affect the access time of the memory. Therefore, it is important that resistance be minimized in an antifuse, which is programmed to a blown state.
Furthermore, as ICs are becoming more dense, it is desirable to decrease the amount of silicon substrate consumed per device, to enable more devices to be formed on a wafer in three dimensions. There is also a need for an improved antifuse structure, which has a lower resistance value in the blown state. This is required to improve IC performance and enable devices to perform faster. It is further desired to form an antifuse structure, in which junction-to-junction leakage and low reverse bias junction breakdown voltages, which have been a problem in the past, are eliminated.
An antifuse structure is formed in an integrated circuit (IC) on a polysilicon layer, which is formed over field oxide, covering non-active device areas of a substrate. By forming an antifuse over field oxide, the amount of silicon substrate consumed is decreased, enabling IC densities to be increased. Furthermore, reverse bias junction breakdown is eliminated at the antifuse because the antifuse is not formed over an n(xe2x88x92) region in a p(xe2x88x92) substrate, as in conventional antifuse structures. This enables the antifuse to be programmed at a faster rate because a wafer level programming pad can be raised above the typical breakdown voltage for faster programming and a tighter resistance distribution after programming. By replacing the n(xe2x88x92) region with a polysilicon layer, a lower resistance IC is formed.
In a further embodiment of the invention, a refractory metal silicide layer is formed over the polysilicon layer, prior to forming an antifuse thereon. The use of refractory metal silicide further decreases the IC resistance. Therefore, programmed antifuses do not inhibit device speed, due to excessive resistance through the antifuse.
In a further embodiment of the invention, the polysilicon or refractory metal silicide layer, over which an antifuse is formed, comprises a bottom conductor layer in an antifuse structure.